1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly, to a configuration for testing semiconductor memory device in a system LSI with a logic and the semiconductor memory device integrated on a common semiconductor substrate.
2. Description of the Background Art
FIG. 36 is a diagram schematically showing an overall configuration of a conventional semiconductor integrated circuit device. In FIG. 36, a semiconductor integrated circuit device 900 includes: a logic 902 performing a prescribed logical processing; and a memory 904 storing at least data necessary for the processing by the logic 902. Logic 902 and memory 904 are integrated on the same semiconductor substrate and logic 902 and memory 904 are interconnected through on-chip interconnection lines 906.
Memory 904 is integrated together with logic 902 on the same semiconductor chip and called an embedded memory. Semiconductor integrated circuit device 900 shown in FIG. 36 generally further includes an analog circuit, a memory of a different kind and other(s), which are integrated with memory 904 and logic 902, to constitute a system LSI implementing one system on one chip.
In semiconductor integrated circuit device 900, on-chip interconnection lines 906 interconnecting logic 902 and memory 904 are smaller in load as compared with an on-board interconnection line or the like, to enable a signal/data to be transferred between logic 902 and memory 904 at high speed. Furthermore, logic 902 and memory 904 are integrated on the same semiconductor substrate and on-chip interconnection lines 906 are coupled with input/output nodes of memory 904. Therefore, with on-chip interconnection lines 906, a data bus width can be widened to transfer data at high speed, due to no restriction by the pitch requirement of pin terminals.
Semiconductor integrated circuit device 900 with logic 902 and memory 904 integrated on the same semiconductor substrate in such a way is widely used as a system LSI in applications such as portable equipment and others.
In such a semiconductor integrated circuit device, in order to secure reliability of a product, it is required to perform a test thereon after fabrication. Logic 902 is coupled to an external device through pin terminals and can be directly accessed from the external device. Memory 904, however, can be externally accessed only through logic 902.
Therefore, in order to enable an external test apparatus to access memory 904 directly, there is usually provided a test interface circuit for accessing directly memory 904 externally.
FIG. 37 is a diagram schematically showing a configuration of a test interface circuit in a conventional semiconductor integrated circuit device. In FIG. 37, the test interface circuit includes: a signal switch circuit 910 for coupling an input signal pad group PDGI and an output pad group PDGO to one of logic 902 and memory 904 according to a test mode instructing signal TST; and a selection circuit (MUX) 912 for selecting one of a signal transferred from signal switch circuit 910 and a signal outputted from logic 902, in accordance with test mode instructing signal TST, to apply the selected one to memory 904. Usually, data read out from memory 904 bypasses selection circuit 912 and are transferred to logic 902 and signal switch circuit 910. This is to done to avoid a signal propagation delay in selection circuit 912 in data read operation.
With signal switch circuit 910 and selection circuit 912 as shown in FIG. 37, the external test apparatus can access memory 904 directly through pad groups PDGI and PDGO, signal switch circuit 910 and selection circuit 912. Therefore, without need of testing memory 904 through logic 902, a test can be performed on characteristics of memory 904, such as whether or not it correctly stores data.
However, since access to memory 904 is made through signal switch circuit 910 and selection circuit 912, a problem arises that for example, set-up and hold times, an access time and the like of memory 904 cannot be correctly measured. That is, the set up and hold times cannot be correctly measured due to an interconnection delay and a skew along this internal transfer path. Furthermore, since data read out from memory 904 is detected externally by an external test apparatus through signal switch circuit 910, such a problem arises that an access time in data reading when logic 902 accesses memory 904 cannot be correctly measured.
Moreover, since there is a difference between an internal data bus width and the number of pin terminals, all data bits of memory 904 cannot be read out in parallel to external pin terminals in data write/read. Therefore, it is required to sequentially select data bits for transference externally in data read, disabling correct measurement of an access time.
Similarly to this, set up and hold times of data in data writing cannot be measured. This problem associated with the set up and hold times occurs not only on data but also on an address signal and a control signal instructing an operation mode in a similar manner.
Memory 904 is generally a synchronous memory operating in synchronization with a clock signal and if the set up and hold times can not be guaranteed, there arises a possibility of failing to correctly take in a command and write data. Moreover, with respect to an access time either, there is a possibility that a high speed operation of logic 902 cannot be insured if correct measurement on an access time cannot be performed in data transfer from memory 904 to logic 902 in a case where data is transferred in synchronization with a high speed clock signal.